Circuit units to be tested, in particular memory chips have internal registers for storing test topologies. Different topologies are necessary in order to simulate “worst case” conditions in a memory array. Registers of this type store test topologies which are used in a subsequent circuit test of the circuit unit to be tested.
It is usually the case that different test topologies are used for testing a circuit unit to be tested, so that it is necessary to change over between different test topologies. In order to change over between different test topologies, it has been proposed:    (i) in each case to reload the content of a register by means of a test mode, or    (ii) to change over between different registers.
The abovementioned concept (i) has the advantage that only one register is required, but has the disadvantage that a pattern sequence (test pattern sequence) has to be interrupted when the register content is being reloaded.
The abovementioned concept (ii) has the advantage that it is possible to switch over during the run time of a test mode, i.e. “on the fly”, but is associated with the disadvantage that it is necessary to use additional external terminal pins for addressing the registers. Furthermore, the disadvantage arises that continual reloading of registers takes up a greater deal of test time such that test costs have increased.
The test costs when testing circuit units to be tested result from the number of circuit units to be tested which can be tested in a specific time, i.e. as a result of the throughput rate. In order to lower test costs, it is possible either to reduce the test times or to increase the number of circuit units to be tested which can be tested in parallel in a test apparatus.
FIG. 2 shows elements of a circuit unit to be tested in a schematic block diagram. A data register R contains various memory units YA, YB, XWR and XRD, four memory units usually being used in the prior art.
These memory units are activated by means of a test mode and in each case loaded with a specific register content. The activation of the test mode and the transfer of the register content are carried out by means of an address and control line A/K, test mode data being input at a test mode data terminal T.
The loading—shown in FIG. 2—of test mode data into a data register R of the circuit unit to be tested has the essential disadvantage that the individual registers YA, YB, XWR and XRD can only be loaded sequentially with the corresponding register contents since, in a register drive unit A, a test mode unit TM can only drive individual register drive units Y1, Y2, X1 and X2 sequentially. The test times and thus the test costs increase in this way since the test mode data for different test topologies always have to be newly loaded sequentially into the data register R.
Therefore, it is an object of the present invention to develop a test apparatus in such a way that a test time when testing circuit units to be tested is reduced.
An essential concept of the invention consists in providing, besides a data register, additional register banks (at least two) in which test mode data sets can be stored beforehand. In the event of a changeover of test topologies, it is then merely necessary for a complete test mode data set to be transferred in parallel from the at least one additional register bank into the data register.